This evening I went to an IEE lecture Computing Without Clocks: From Lab to Exploitation. This was by Prof Steve Furber of Manchester University. Famously he developed a range of ARM like asynchronous processors, the Amulet series.

The talk was rahter low on technical detail but it was interesting that they think the future lies in asynchronous networks between IP blocks on a chip. Adapters are placed on all synchronous logic blocks and a packet switch interconnect is auto-generated to a required speicifcation. I know from my digital design experience that at least 2 synchronising flops are needed to change to an asynchronoush clock domain. So for blockA <-> asynch bus <-> blockB these penalties can be costly. I am guessing that they can do better than this, either by the design of the adapters or by sometimes taking less cycles instead of always taking penalties.

The biggest advantage (IMHPO was that unlike the efforts needed in clocked system to implement voltage and frequency scaling, in an un-clockedcircuit there is no clock and the voltage can be varied all the time, with the caveat that the rate at which results are produced might change.